As is known, all currently marketed types of memory read array cells by comparing the content of the cells with a known content of a selected reference cell. A memory of this type is illustrated in FIG. 1. This figure shows a memory cell 1, whose content is to be read, connected (together with other cells not shown) to a bit line 2. Bit line 2 is connected to a selection circuit 4 which is in turn connected to an array branch 3 forming part of the reading device and comprising a current/voltage converter 5. Selection circuit 4 comprises pass transistors, and receives a decoding signal DEC for selectively enabling read operations by connecting/disconnecting bit line 2 to/from converter 5. Converter 5 comprises a precharge circuit 6 and a load 7 connected in series between selection circuit 4 and a supply line V.sub.CC. Node 8, positioned between precharge circuit 6 and load 7, constitutes the output of array branch 3 and is connected to one input of a single- or two-stage sense amplifier 10 having another input connected to the output 11 of a reference branch 12 with the same structure as array branch 3.
More specifically, reference branch 12 comprises a current/voltage converter 14 and a precharge circuit 16. Converter 14 comprises a load 15 connected between supply line V.sub.CC and precharge circuit 16. The precharge circuit 16 is connected to a reference cell 17 (whose content, or state, is known) via a selection simulating circuit 18 also comprising a pass transistor, the gate terminal of which is so biased as to maintain an active connection between reference cell 17 and converter 14.
In known manner, the memory array comprises n array reading branches 3 (one for each output of the reading device plus a redundancy branch) and one reference branch 12.
In the FIG. 1 arrangement, converters 5, 14 detect the currents through read cell 1 and reference cell 17 respectively, and convert them into a voltage. More specifically, the current along bit line 2, and hence through load 7, depends on the state (programmed or erased) of cell 1, whereas the current in reference branch 12 is known; and the two voltages at outputs 8, 11 are then compared in amplifier 10.
For the array cells to be read correctly, the reference branch, with the exception of the load must be as similar as possible to the array branch. The reference branch load is normally formed by two or more identical current paths to the supply, so that, if the read cell is erased, the reference current (through reference cell 17) equals or is twice or a multiple of the current through the array branch.
According to one known solution, the load of all the array branches is formed by a diode-connected MOS transistor, and the reference branch comprises two MOS transistors of the same type as the array branch transistors, also diode-connected, and connected in parallel between node 11 and supply line V.sub.CC. Also, as some situations require that one of the current paths of the reference branch be turned off, so that the reference current equals the current through an erased array cell, the switchable current path typically includes a controlled switch in the form of a MOS transistor. This MOS transistor is typically connected in series with the respective load transistor. To achieve a correct relationship between the reference and array branch currents, the current paths must be the same, so similar transistors (simulating controlled switches and of the same size and characteristics) must be provided along the other current path of the reference branch and along each array branch, which additional transistors are so biased as to be permanently on.
As the additional transistors must be large to operate effectively as switches, and must be provided in all the array branches, the above solution is extremely cumbersome.